In display controllers supporting layers or sprites, output images displayed, may be generated by activating said layers or sprites in the output image. The display is refreshed at a selected refresh rate, e.g. several times per second, often requiring relatively high speed data transfer from for example a memory to a processing unit. While the display is refreshed, said layers are activated and deactivated.
In order to reduce the latency requirement of the display controller, buffers are utilized to buffer data between the memory and the processing unit. The buffers pre-fetch the data from the memory and store the data temporarily therein until the processing unit can process the incoming data. New data can be fetched from the memory and stored in the buffers after the incoming data is processed. While the data is fetched, stored and processed, the display or a portion of the display is refreshed. Notoriously, the buffers have limited memory capacity and are costly components of the system.
In order to overcome these limitations several solutions have been proposed in literature. For example, in U.S. Pat. No. 5,841,722, a variable sized first-in first-out (FIFO) buffer is disclosed. The size of the disclosed FIFO is changed in accordance with how much data is present to be passed between a transferring system and a receiving system. The disclosed FIFO uses an external random access memory (RAM) of the system as an overflow memory when the FIFO buffer is temporarily full. A controller unit interfacing the FIFO buffer to the RAM performs access to the RAM.
However, U.S. Pat. No. 5,841,722 utilizes a RAM and a controller unit to read and write data in blocks when the FIFO is temporarily full, increasing system complexity and overall access time especially in systems, e.g. display systems, where relatively high speed data transfer is required.